digital multiplexer

英 [ˈdɪdʒɪtl ˈmʌltɪplɛksə] 美 [ˈdɪdʒɪtl ˈmʌltiˌplɛksər]

网络  数字多工处理器; 数字复接器; 数字复接系统由复接器; 数字多路选择器; 数字复用器

计算机



双语例句

  1. Design of multi-channel digital signal multiplexer/ demultiplexer based on FPGA
    基于FPGA的多路数字信号复分接器的设计
  2. An on-board digital multiplexer allows the user to access data from the various stages of the decimation filter.
    用户可以通过片上数字多路复用器访问各级抽取滤波器中的数据。
  3. The Digital Multiplexer in Power Line Carrier
    电力线载波数字复接器
  4. Research and Implementation of High-Speed Digital Multiplexer
    高速数据复接器的研究与实现
  5. By using the method, the digital multiplexer networks being designed can be simplified to minimal tree-type networks.
    这种方法可以使待设计的数字多路选择器网络简化到最小树形网络。
  6. On the basis of analysis of the expansion form for the logic functions with respect to its some variations, theory and method of optimal design for digital multiplexer two-level logic networks are discussed by using Boolean algebra operations in this paper.
    基于逻辑函数按变量展开式的分析,利用布尔代数运算,讨论了数字多路选择器二级逻辑网络的最优化设计的理论和方法。
  7. The content mostly refers to signal pre-processing and post-processing, signal synchronization, digital multiplexer, and system integration.
    主要包括的相关内容有:信号的预处理与后续处理,信号同步,数字复接,以及系统合成等内容。
  8. This design is implemented by digital synchronous ways, and can accomplish the 7 ( can expand to N) routes E1 data's demultiplexer and multiplexer.
    该分接复用器电路用纯数字同步方式实现,可完成SDH系统接口电路中7路(可扩展成N路)E1数据流的分接和复用。
  9. This paper applies the FPGA technology in digital TV system, makes research on digital TV front-end system key equipment& MPEG-2 transport stream multiplexer, and FPGA modeling and implement.
    本论文将迅速发展的FPGA技术应用于数字电视系统中,研究探讨了数字电视前端系统中的关键设备&传输流复用器的FPGA建模和实现,以及相关的关键技术。
  10. An Algebraic Method for the Design of Digital Multiplexer Networks
    数字多路选择器网络设计的一种代数方法
  11. Optimal Design for Digital Multiplexer Single-Level and Two-Level Logic Networks ⅱ
    数字多路选择器单级及二级逻辑网络的最优化设计Ⅱ
  12. The subject is mainly accomplish a digital multiplexer by FPGA.
    本课题主要是用FPGA实现一个数字复接器。
  13. Design of Frame Synchronous Digital Multiplexer System with FPGA
    基于FPGA的帧同步数字复接系统设计
  14. Against the background of the application of Synchronous Digital Hierarchy ( SDH), the paper mainly discusses the design principles and chief techniques of an Add-Drop Multiplexer ( ADM), one of the SDH equipments.
    本文以同步数字体系(SDH)应用为背景,论述了SDH分插复用器(ADM)系统的原理与设计方法。
  15. This thesis has given out a detailed introduction on the Research& Developmentof the Digital Multiplexer which is used in the power line as a part of the DPLC ( Digital Power Line Carrier).
    论文针对电力载波数据复接器+电力线载波机的DPLC(数字式电力线载波机)解决方案中的电力载波数据复接器的研制开发做了详细说明。
  16. The highly development of digital products based on MPEG-2 with usable transmittal bandwidth decreasing rapidly have resulted in the widely demand for the multiplexer and the de-multiplexer.
    以MPEG-2为载体的数字化产品(如DVB、非线性编辑,卫星直播等)的飞速发展以及传输频带的日益紧张导致了复用器、解复用器的大量需求。
  17. Digital video has been transmitted using channels that have constant channel rate, so there always need a output buffer between the video encoder and the channel multiplexer when the encoder operates on the CBR mode.
    视频编码器工作于CBR模式时,通常需要在编解码器和信道之间放置一个缓冲器(Bufer),并由相应的码率控制单元调整量化参数以避免缓冲器产生溢出。
  18. This paper mainly discusses some theory about digital multiplexer, the paper's difference with other multiplexer, and how to implement the design using the FPGA.
    本文主要讨论了现阶段数字复接的一些相关理论,本设计的具体特点,以及如何通过FPGA对该系统进行实现。
  19. Theory and Algorithm for the Design of Digital Multiplexer Tree-Type Networks
    数字多路选择器树形网络设计理论和算法
  20. Design and Implementation of Digital Video Multi-program Multiplexer Based on PES Streams
    基于PES流的数字视频多节目复用器的设计和实现
  21. In this paper, we introduce the design and implementation of digital interface for power line carrier digital multiplexer demultiplexer.
    这里重点介绍数字复接设备中数据接口的设计方案。
  22. Digital multiplexer and matrix equation in designing combinational logic circuit
    采用数据选择器和矩阵方程法设计组合逻辑电路
  23. In order to put device model in practice, two high speed digital chips are designed: 2Gb/ s 16:1 multiplexer and 2Gb/ s 1:16 demultiplexer.
    作为器件模型的实际运用,文中设计了两块高速数字电路芯片:2Gb/s16:1复接器和2Gb/s1:16分接器。
  24. By using Boolean algebraic operations, an algebraic method for finding the reduced disjoint SOP forms of Boolean functions has been developed and an algebraic method for designing the digital multiplexer networks based on the SOP forms is proposed in this paper.
    利用布尔代数运算,导出了求布尔函数的简化的不相交SOP形式的一种代数方法,提出了基于这种SOP形式的数字多路选择器网络设计的一种代数方法。